STM32F411系统时钟是多少，STM32固件库 ADC默认时钟是多少

来源：整理时间：2024-01-15 07:43:36 编辑：亚灵电子网手机版

本文目录一览

1，STM32固件库 ADC默认时钟是多少
2，STM32固件库 ADC默认时钟是多少
3，stm32 systick的默认时钟是多少
4，STM32的系统默认时钟是多少
5，stm32默认时钟是多少
6，STM32的系统默认时钟是多少
7，STM32F103的APB1时钟频率最大为多少
8，STM32里系统时钟
9，stm32f407 初始时钟是多少怎么改

1，STM32固件库 ADC默认时钟是多少

STM32F10x系列ADC最高时钟不超过14MHz。如果使用固件库，就用函数RCC_ADCCLKConfig()来设置ADC的工作时钟，根据系统工作频率来分频，比如72MHz时就需要6分频：RCC_ADCCLKConfig(RCC_PCLK2_Div6)。

STM32固件库 ADC默认时钟是多少

2，STM32固件库 ADC默认时钟是多少

STM32固件库 ADC默认时钟是多少

3，stm32 systick的默认时钟是多少

默认时钟是系统时钟，比如你倍频到72M，时钟源就是72M而不是它的8分频

systick是慢速的，一般用32k的外部晶振，用来计时sysclk是主时钟，就是给内核以及大多数外设的那个最高72m的。hclk是高速外设时钟，是给外部设备的，比如内存，flash

stm32 systick的默认时钟是多少

4，STM32的系统默认时钟是多少

STM32系统的时钟一般有三种HSI,内部高速时钟,默认8MHZ,如果你的程序不做任何处理,系统默认的就是8MHz,还有外部晶振或者外部时钟,普通型最大不超过16MHz,互联型不超过25MHz,还有一个PLL,从HSI或者HSE里吸取时钟,倍频成最大72MHz综述,如果你的程序不做任何处理,就是8MH是

5，stm32默认时钟是多少

stm32F1系类最大72Mhz 你可以超频用但是不一定能稳定可靠工作比方说你用8M晶振配置按照72M主频算，直接换成10M晶振主频自然就是 90MFlash Leancy 设到最大应该可以比72Mhz 高一些，另外 APB1分频要小于等于36MHz，要用usb的话必须是48或72

stm32系统的时钟一般有三种hsi,内部高速时钟,默认8mhz,如果你的程序不做任何处理,系统默认的就是8mhz,还有外部晶振或者外部时钟,普通型最大不超过16mhz,互联型不超过25mhz,还有一个pll,从hsi或者hse里吸取时钟,倍频成最大72mhz综述,如果你的程序不做任何处理,就是8mh是

6，STM32的系统默认时钟是多少

/*!< At this stage the microcontroller clock setting is already configured, this is done through SystemInit() function which is called from startupfile (startup_stm32f10x_xx.s) before to branch to application main.To reconfigure the default setting of SystemInit() function, refer tosystem_stm32f10x.c file*/ 然后你再去看看 SystemInit()这个函数是怎么配置的吧。看完再说。这个是标准库里面的例程主函数里的第一句话。

7，STM32F103的APB1时钟频率最大为多少

APB1最大频率是36Mhz，这个在初始化的时候就已经设置了的，如果用库函数默认就是36Mhz，在main函数运行前就设置了，一般可以不管。如果自己操作寄存器就不一定了。然后psc的问题：其实里面有两个分频的概念，APB预分频和计数器时钟频率（CK_PSC）的关系指的是AHB分频得到APB1，一般AHB取最大72Mhz，所以APB1是AHB的2分频，既然不是1分频，所以计数器时钟就是APB1的2倍了。而最终定时器的时钟频率(CK_CNT)是对CK_PSC进行psc值的分频得到的，这个值就是我们用来定时计算的数值。图中CK_PSC就是从APB1得到的时钟，预分频控制寄存器的值就是PSC里面的值，而CK_CNT就是分频最终得到的值。STM32F103的APB1时钟频率最大为多少

8，STM32里系统时钟

这得看你程序 RCC那块的配置，//PLL设置 SYSCLK/1 * 9 = 8*1*9 = 72MHzRCC_PLLConfig(RCC_PLLSource_HSE_Div1, RCC_PLLMul_9);//启动PLLRCC_PLLCmd(ENABLE);标配是外接8Mhz，内部9倍频，平常的学习，工作都满足了！

不可能出现这种情况吧？STM32F10X系列的，外部晶振最大只能到16MPLL的倍频值只能是整数，结果是系统时钟 = 晶振 * 倍频值所以倍频值 = 系统时钟 / 晶振只能是整数，不能带小数点。所以，即使STM32F10X允许你用25M，你也得不到72M，最大只能到50M

rcc_apb2periphclockcmd(rcc_apb2periph_gpiog, enable); 只是开了gpiog时钟，配置gpiog管脚前必须开此systeminit();系统初始化，开芯片内部时钟等等，完全不是一个概念

9，stm32f407 初始时钟是多少怎么改

STM32启动时默认为内部RC震荡所以在使用的时候，首先要对时钟进行初始化等待外部晶振稳定后然后才对外部晶振进行分频或者倍频最后才是对APB总线时钟及模块时钟进行配置。

楼上的用起来也有点麻烦，用我这个吧，C文件：#include "stm32f4xx.h"#include "sysclk.h"unsigned char SysClockSet(unsigned char OSC, unsigned char Clock) unsigned int temp = 0, PLLM = 0, PLLN = 0, PLLP = 0, PLLQ = 0; unsigned int OSC_Sta; unsigned int OSC_VALUE = HSI_VALUE; unsigned int OSC_RDY = RCC_CR_HSIRDY; unsigned int OSC_ON = RCC_CR_HSION; unsigned char OSC_ERROR = HSI_error; unsigned int OSC_OK = HSI_OK; unsigned int OSC_SW = RCC_CFGR_SW_HSI; unsigned int OSC_SWS = RCC_CFGR_SWS_HSI; unsigned int OSC_SRC = RCC_PLLCFGR_PLLSRC_HSI; if(OSC == HSE) OSC_VALUE = HSE_VALUE; OSC_RDY = RCC_CR_HSERDY; OSC_ON = RCC_CR_HSEON; OSC_ERROR = HSE_error; OSC_OK = HSE_OK; OSC_SW = RCC_CFGR_SW_HSE; OSC_SWS = RCC_CFGR_SWS_HSE; OSC_SRC = RCC_PLLCFGR_PLLSRC_HSE; } else if(OSC != HSI) return(Parameter_error); switch (Clock) case 0 : PLLM = (OSC_VALUE/1000000); PLLN = 96; PLLP = 8; PLLQ = 2; break; //12MHz case 1 : PLLM = (OSC_VALUE/1000000); PLLN = 96; PLLP = 6; PLLQ = 2; break; //16MHz case 2 : PLLM = (OSC_VALUE/2000000); PLLN = 72; PLLP = 8; PLLQ = 3; break; //18MHz case 3 : PLLM = (OSC_VALUE/2000000); PLLN = 96; PLLP = 8; PLLQ = 4; break; //24MHz case 4 : PLLM = (OSC_VALUE/2000000); PLLN = 120; PLLP = 8; PLLQ = 5; break; //30MHz case 5 : PLLM = (OSC_VALUE/2000000); PLLN = 96; PLLP = 6; PLLQ = 4; break; //32MHz case 6 : PLLM = (OSC_VALUE/2000000); PLLN = 144; PLLP = 8; PLLQ = 6; break; //36MHz case 7 : PLLM = (OSC_VALUE/2000000); PLLN = 120; PLLP = 6; PLLQ = 5; break; //40MHz case 8 : PLLM = (OSC_VALUE/2000000); PLLN = 168; PLLP = 8; PLLQ = 7; break; //42MHz case 9 : PLLM = (OSC_VALUE/2000000); PLLN = 192; PLLP = 8; PLLQ = 8; break; //48MHz case 10: PLLM = (OSC_VALUE/2000000); PLLN = 216; PLLP = 8; PLLQ = 9; break; //54MHz case 11: PLLM = (OSC_VALUE/2000000); PLLN = 168; PLLP = 6; PLLQ = 7; break; //56MHz case 12: PLLM = (OSC_VALUE/2000000); PLLN = 120; PLLP = 4; PLLQ = 5; break; //60MHz case 13: PLLM = (OSC_VALUE/2000000); PLLN = 192; PLLP = 6; PLLQ = 8; break; //64MHz case 14: PLLM = (OSC_VALUE/2000000); PLLN = 144; PLLP = 4; PLLQ = 6; break; //72MHz case 15: PLLM = (OSC_VALUE/2000000); PLLN = 240; PLLP = 6; PLLQ = 10; break; //80MHz case 16: PLLM = (OSC_VALUE/2000000); PLLN = 168; PLLP = 4; PLLQ = 7; break; //84MHz case 17: PLLM = (OSC_VALUE/2000000); PLLN = 192; PLLP = 4; PLLQ = 8; break; //96MHz case 18: PLLM = (OSC_VALUE/2000000); PLLN = 216; PLLP = 4; PLLQ = 9; break; //108MHz case 19: PLLM = (OSC_VALUE/2000000); PLLN = 120; PLLP = 2; PLLQ = 5; break; //120MHz case 20: PLLM = (OSC_VALUE/2000000); PLLN = 144; PLLP = 2; PLLQ = 6; break; //144MHz case 21: PLLM = (OSC_VALUE/2000000); PLLN = 168; PLLP = 2; PLLQ = 7; break; //168MHz case 22: PLLM = (OSC_VALUE/2000000); PLLN = 192; PLLP = 2; PLLQ = 8; break; //192MHz case 23: PLLM = (OSC_VALUE/2000000); PLLN = 216; PLLP = 2; PLLQ = 9; break; //216MHz case 24: PLLM = (OSC_VALUE/2000000); PLLN = 240; PLLP = 2; PLLQ = 10; break; //240MHz// case 25: PLLM = (OSC_VALUE/2000000); PLLN = 260; PLLP = 2; PLLQ = 11; break; //260MHz default: PLLM = (OSC_VALUE/2000000); PLLN = 240; PLLP = 2; PLLQ = 10; break; //240MHz } //如果时钟没有稳定，则重新启动时钟并等待稳定 OSC_Sta = RCC->CR & OSC_RDY; if(OSC_Sta == 0) RCC->CR |= OSC_ON; do OSC_Sta = RCC->CR & OSC_RDY; temp++; }while((OSC_Sta == 0) && (temp < 0x0600)); if(OSC_Sta == 0)return(OSC_ERROR); //超时错误 } //切换系统时钟为对应晶振并等待稳定 RCC->CFGR &= (~(RCC_CFGR_SW)); RCC->CFGR |= OSC_SW; while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != OSC_SWS); //配置PLL RCC->CR &= (~(RCC_CR_PLLON)); //先关闭PLL RCC->CR &= (~(RCC_CR_PLLI2SON)); //关闭PLLI2S RCC->PLLCFGR = PLLM | (PLLN << 6) | (((PLLP >> 1) -1) << 16) | (PLLQ << 24) | (OSC_SRC); //启用PLL，并等待稳定 RCC->CR |= RCC_CR_PLLON; while((RCC->CR & RCC_CR_PLLRDY) == 0); //启用PLLI2S，并等待稳定 RCC->CR |= RCC_CR_PLLI2SON; while((RCC->CR & RCC_CR_PLLI2SRDY) == 0); //切换系统时钟为PLL并等待稳定 RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW)); RCC->CFGR |= RCC_CFGR_SW_PLL; while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL); return(OSC_OK);}uint32_t SysClockGet(void) uint32_t PLLM = 0, PLLN = 0, PLLP = 0, PLLSRC = 0; if ((RCC->CFGR & RCC_CFGR_SWS ) == RCC_CFGR_SWS_HSE) return HSE_VALUE; else if ((RCC->CFGR & RCC_CFGR_SWS ) == RCC_CFGR_SWS_HSI) return HSI_VALUE; else PLLM = RCC->PLLCFGR & RCC_PLLCFGR_PLLM; PLLN = ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN)>>6); PLLP = ((((RCC->PLLCFGR & RCC_PLLCFGR_PLLP)>>16)+1)<<1); PLLSRC = RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC; if(PLLSRC == 0) return (((HSI_VALUE * PLLN) / PLLM )/ PLLP); else return (((HSE_VALUE * PLLN) / PLLM )/ PLLP); }}